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In computing, floating point operations per second (FLOPS, flops or flop/s) is a measure of computer performance, useful in fields of scientific computations that require floating-point calculations. For such cases it is a more accurate measure than measuring instructions per second.
The similar term FLOP is often used for floating-point operation, for example as a unit of counting floating-point operations carried out by an algorithm or computer hardware.
Floating-point arithmetic is needed for very large or very small real numbers, or computations that require a large dynamic range. Floating-point representation is similar to scientific notation, except everything is carried out in base two, rather than base ten. The encoding scheme stores the sign, the exponent (in base two for Cray and VAX, base two or ten for IEEE floating point formats, and base 16 for IBM Floating Point Architecture) and the Significand (number after the radix point). While several similar formats are in use, the most common is ANSI/IEEE Std. 754-1985. This standard defines the format for 32-bit numbers called single precision, as well as 64-bit numbers called double precision and longer numbers called extended precision (used for intermediate results). Floating-point representations can support a much wider range of values than fixed-point, with the ability to represent very small numbers and very large numbers.
The exponentiation inherent in floating-point computation assures a much larger dynamic range – the largest and smallest numbers that can be represented – which is especially important when processing data sets which are extremely large or where the range may be unpredictable. As such, floating-point processors are ideally suited for computationally intensive applications.
FLOPS and MIPS are units of measure for the numerical computing performance of a computer. Floating-point operations are typically used in fields such as scientific computational research. The unit MIPS measures integer performance of a computer. Examples of integer operation include data movement (A to B) or value testing (If A = B, then C). MIPS as a performance benchmark is adequate when a computer is used in database queries, word processing, spreadsheets, or to run multiple virtual operating systems. Frank H. McMahon, of the Lawrence Livermore National Laboratory, invented the terms FLOPS and MFLOPS (megaFLOPS) so that he could compare the supercomputers of the day by the number of floating-point calculations they performed per second. This was much better than using the prevalent MIPS to compare computers as this statistic usually had little bearing on the arithmetic capability of the machine.
FLOPS can be calculated using this equation:
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|CPU Family||Double precision||Single precision|
|Intel Core and Intel Nehalem||4 DP FLOPs/cycle: 2-wide SSE2 addition + 2-wide SSE2 multiplication||8 SP FLOPs/cycle: 4-wide SSE addition + 4-wide SSE multiplication|
|Intel Sandy Bridge and Intel Ivy Bridge||8 DP FLOPs/cycle: 4-wide AVX addition + 4-wide AVX multiplication||16 SP FLOPs/cycle: 8-wide AVX addition + 8-wide AVX multiplication|
|Intel Haswell, Intel Broadwell and Intel Skylake||16 DP FLOPs/cycle: two 4-wide FMA instructions||32 SP FLOPs/cycle: two 8-wide FMA instructions|
|Intel Xeon Skylake (AVX-512)||16 or 32 DP FLOPs/cycle: one or two 8-wide FMA instructions (depends on SKU)||32 or 64 SP FLOPs/cycle: one or two 16-wide FMA instructions (depends on SKU)|
|AMD K10||4 DP FLOPs/cycle: 2-wide SSE2 addition + 2-wide SSE2 multiplication||8 SP FLOPs/cycle: 4-wide SSE addition + 4-wide SSE multiplication|
|AMD Bulldozer, AMD Piledriver and AMD Steamroller,
per module (two cores)
|8 DP FLOPs/cycle: 4-wide FMA||16 SP FLOPs/cycle: 8-wide FMA|
|AMD Ryzen (per core)||8 DP FLOPs/cycle: pair 2-wide FMA instructions||16 SP FLOPs/cycle: pair 4-wide FMA instructions|
|Intel Atom (Bonnell, Saltwell, Silvermont and Goldmont)||2 DP FLOPs/cycle: scalar SSE2 addition + scalar SSE2 multiplication every other cycle||
8 SP FLOPs/cycle: 4-wide SSE addition + 4-wide SSE multiplication every other cycle
|AMD Bobcat||2 DP FLOPs/cycle: scalar SSE2 addition + scalar SSE2 multiplication every other cycle||4 SP FLOPs/cycle: 4-wide SSE addition every other cycle + 4-wide SSE multiplication every other cycle|
|AMD Jaguar||4 DP FLOPs/cycle: 2-wide SSE2 addition + 2-wide SSE2 multiplication||8 SP FLOPs/cycle: 8-wide AVX addition every other cycle + 8-wide AVX multiplication every other cycle|
|ARM Cortex-A7||1 FLOPs/cycle: scalar addition + scalar multiplication every other cycle||8 SP FLOPs/cycle: 4-wide NEON addition every other cycle + 4-wide NEON multiplication every other cycle|
|ARM Cortex-A9||1 FLOPs/cycle: scalar addition + scalar multiplication every other cycle||8 SP FLOPs/cycle: 4-wide NEON addition every other cycle + 4-wide NEON multiplication every other cycle|
|ARM Cortex-A15||1 DP FLOPs/cycle: scalar FMA or scalar multiply-add||8 SP FLOPs/cycle: 4-wide NEONv2 FMA or 4-wide NEON multiply-add|
|ARM Cortex-A32||2 DP FLOPs/cycle: scalar FMA or scalar multiply-add||8 SP FLOPs/cycle: 4-wide NEONv2 FMA or 4-wide NEON multiply-add|
|ARM Cortex-A35||2 DP FLOPs/cycle: scalar FMA or scalar multiply-add||8 SP FLOPs/cycle: 4-wide NEONv2 FMA or 4-wide NEON multiply-add|
|ARM Cortex-A53||4 DP FLOPs/cycle: scalar FMA or scalar multiply-add||8 SP FLOPs/cycle: 4-wide NEONv2 FMA or 4-wide NEON multiply-add|
|ARM Cortex-A57||4 DP FLOPs/cycle: two scalar FMA or one 2-wide FMA||8 SP FLOPs/cycle: 4-wide NEONv2 FMA or 4-wide NEON multiply-add|
|ARM Cortex-A72||2 DP FLOPs/cycle: scalar FMA or scalar multiply-add||8 SP FLOPs/cycle: 4-wide NEONv2 FMA or 4-wide NEON multiply-add|
|Qualcomm Krait||1 DP FLOPs/cycle: scalar FMA or scalar multiply-add||8 SP FLOPs/cycle: 4-wide NEONv2 FMA or 4-wide NEON multiply-add|
|Qualcomm Kryo||2 DP FLOPs/cycle: scalar FMA or scalar multiply-add||8 SP FLOPs/cycle: 4-wide NEONv2 FMA or 4-wide NEON multiply-add|
|IBM PowerPC A2 (Blue Gene/Q), per core||8 DP FLOPs/cycle: 4-wide QPX FMA every cycle (SP elements are extended to DP and processed on the same units)|
|IBM PowerPC A2 (Blue Gene/Q), per thread||4 DP FLOPs/cycle: 4-wide QPX FMA every other cycle (SP elements are extended to DP and processed on the same units)|
|Intel Xeon Phi (Knights Corner), per core||16 DP FLOPs/cycle: 8-wide FMA every cycle||32 SP FLOPs/cycle: 16-wide FMA every cycle|
|Intel Xeon Phi (Knights Corner), per thread (two per core)||8 DP FLOPs/cycle: 8-wide FMA every other cycle||16 SP FLOPs/cycle: 16-wide FMA every other cycle|
|Intel Xeon Phi (Knights Landing)||32 DP FLOPs/cycle: two 8-wide FMA instructions||64 SP FLOPs/cycle: two 16-wide FMA instructions|
|Standard GPU||Different||2 SP FLOPs/cycle|
In June 1997, Intel's ASCI Red was the world's first computer to achieve one teraFLOPS and beyond. Sandia director Bill Camp said that ASCI Red had the best reliability of any supercomputer ever built, and "was supercomputing's high-water mark in longevity, price, and performance".
For comparison, a handheld calculator performs relatively few FLOPS. A computer response time below 0.1 second in a calculation context is usually perceived as instantaneous by a human operator, so a simple calculator needs only about 10 FLOPS to be considered functional.
In June 2006, a new computer was announced by Japanese research institute RIKEN, the MDGRAPE-3. The computer's performance tops out at one petaFLOPS, almost two times faster than the Blue Gene/L, but MDGRAPE-3 is not a general purpose computer, which is why it does not appear in the Top500.org list. It has special-purpose pipelines for simulating molecular dynamics.
By 2007, Intel Corporation unveiled the experimental multi-core POLARIS chip, which achieves 1 teraFLOPS at 3.13 GHz. The 80-core chip can raise this result to 2 teraFLOPS at 6.26 GHz, although the thermal dissipation at this frequency exceeds 190 watts.
On June 26, 2007, IBM announced the second generation of its top supercomputer, dubbed Blue Gene/P and designed to continuously operate at speeds exceeding one petaFLOPS. When configured to do so, it can reach speeds in excess of three petaFLOPS.
On October 25, 2007, NEC Corporation of Japan issued a press release announcing its SX series model SX-9, claiming it to be the world's fastest vector supercomputer. The SX-9 features the first CPU capable of a peak vector performance of 102.4 gigaFLOPS per single core.
On February 4, 2008, the NSF and the University of Texas at Austin opened full scale research runs on an AMD, Sun supercomputer named Ranger, the most powerful supercomputing system in the world for open science research, which operates at sustained speed of 0.5 petaFLOPS.
On May 25, 2008, an American supercomputer built by IBM, named 'Roadrunner', reached the computing milestone of one petaFLOPS. It headed the June 2008 and November 2008 TOP500 list of the most powerful supercomputers (excluding grid computers). The computer is located at Los Alamos National Laboratory in New Mexico. The computer's name refers to the New Mexico state bird, the greater roadrunner (Geococcyx californianus).
In June 2008, AMD released ATI Radeon HD 4800 series, which are reported to be the first GPUs to achieve one teraFLOPS. On August 12, 2008, AMD released the ATI Radeon HD 4870X2 graphics card with two Radeon R770 GPUs totaling 2.4 teraFLOPS.
In November 2008, an upgrade to the Cray XT Jaguar supercomputer at the Department of Energy's (DOE's) Oak Ridge National Laboratory (ORNL) raised the system's computing power to a peak 1.64 petaFLOPS, making Jaguar the world's first petaFLOPS system dedicated to open research. In early 2009 the supercomputer was named after a mythical creature, Kraken. Kraken was declared the world's fastest university-managed supercomputer and sixth fastest overall in the 2009 TOP500 list. In 2010 Kraken was upgraded and can operate faster and is more powerful.
As of 2010[update] the fastest six-core PC processor reaches 109 gigaFLOPS (Intel Core i7 980 XE) in double precision calculations. GPUs are considerably more powerful. For example, Nvidia Tesla C2050 GPU computing processors perform around 515 gigaFLOPS in double precision calculations, and the AMD FireStream 9270 peaks at 240 gigaFLOPS. In single precision performance, Nvidia Tesla C2050 computing processors perform around 1.03 teraFLOPS and the AMD FireStream 9270 cards peak at 1.2 teraFLOPS. Both Nvidia and AMD's consumer gaming GPUs may reach higher FLOPS. For example, AMD's HemlockXT 5970 reaches 928 gigaFLOPS in double precision calculations with two GPUs on board and the Nvidia GTX 480 reaches 672 gigaFLOPS with one GPU on board.
In November 2011, it was announced that Japan had achieved 10.51 petaFLOPS with its K computer. It is still under development and software performance tuning is currently underway. It has 88,128 SPARC64 VIIIfx processors in 864 racks, with theoretical performance of 11.28 petaFLOPS. It is named after the Japanese word "kei", which stands for 10 quadrillion, corresponding to the target speed of 10 petaFLOPS.
On November 15, 2011, Intel demonstrated a single x86-based processor, code-named "Knights Corner", sustaining more than a teraFLOPS on a wide range of DGEMM operations. Intel emphasized during the demonstration that this was a sustained teraFLOPS (not "raw teraFLOPS" used by others to get higher but less meaningful numbers), and that it was the first general purpose processor to ever cross a teraFLOPS.
On June 18, 2012, IBM's Sequoia supercomputer system, based at the U.S. Lawrence Livermore National Laboratory (LLNL), reached 16 petaFLOPS, setting the world record and claiming first place in the latest TOP500 list.
On November 12, 2012, the TOP500 list certified Titan as the world's fastest supercomputer per the LINPACK benchmark, at 17.59 petaFLOPS. It was developed by Cray Inc. at the Oak Ridge National Laboratory and combines AMD Opteron processors with "Kepler" NVIDIA Tesla graphic processing unit (GPU) technologies.
On June 20, 2016, China's Sunway TaihuLight was ranked the world's fastest with 93 petaFLOPS on the LINPACK benchmark (out of 125 peak petaFLOPS). The system, which is almost exclusively based on technology developed in China, is installed at the National Supercomputing Center in Wuxi, and represents more performance than the next five most powerful systems on the TOP500 list combined.
In June 2018, Summit, an IBM-built supercomputer now running at the Department of Energy’s (DOE) Oak Ridge National Laboratory (ORNL), captured the number one spot with a performance of 122.3 petaflops on High Performance Linpack (HPL), the benchmark used to rank the TOP500 list. Summit has 4,356 nodes, each one equipped with two 22-core Power9 CPUs, and six NVIDIA Tesla V100 GPUs.
Given the current speed of progress, supercomputers are projected to reach 1 exaFLOPS (EFLOPS) in 2018. Cray, Inc. announced in December 2009 a plan to build a 1 EFLOPS supercomputer before 2020. Erik P. DeBenedictis of Sandia National Laboratories theorizes that a zettaFLOPS (ZFLOPS) computer is required to accomplish full weather modeling of two week time span. Such systems might be built around 2030.
|Date||Approximate cost per GFLOPS||Approximate cost per GFLOPS (2017 US dollars)||Approximate cost per TFLOPS (2017 US dollars)||Platform providing the lowest cost per GFLOPS||Comments|
|1961||$18.7 billion||$153.1 billion||$153.1 trillion||About 2400 IBM 7030 Stretch supercomputers costing $7.78 million each||The IBM 7030 Stretch performs one floating-point multiply every 2.4 microseconds.|
|1984||$18,750,000||$44,170,000||$44.2 billion||Cray X-MP/48||$15,000,000 / 0.8 GFLOPS|
|1997||$30,000||$46,000||$46,000,000||Two 16-processor Beowulf clusters with Pentium Pro microprocessors|
|April 2000||$1,000||$1,440||$1,440,000||Bunyip Beowulf cluster||Bunyip was the first sub-US$1/MFLOPS computing technology. It won the Gordon Bell Prize in 2000.|
|May 2000||$640||$922||$922,000||KLAT2||KLAT2 was the first computing technology which scaled to large applications while staying under US-$1/MFLOPS.|
|August 2003||$82||$109||$109,000||KASY0||KASY0 was the first sub-US$100/GFLOPS computing technology.|
|August 2007||$48||$57||$57,000||Microwulf||As of August 2007, this 26.25 GFLOPS "personal" Beowulf cluster can be built for $1256.|
|March 2011||$1.80||$1.98||$1,980||HPU4Science||This $30,000 cluster was built using only commercially available "gamer" grade hardware.|
|August 2012||$0.75||$0.80||$800||Quad AMD Radeon 7970 GHz System||A quad AMD Radeon 7970 desktop computer reaching 16 TFLOPS of single-precision, 4 TFLOPS of double-precision computing performance. Total system cost was $3000; Built using only commercially available hardware.|
|June 2013||$0.22||$0.23||$230||Sony PlayStation 4||The Sony PlayStation 4 is listed as having a peak performance of 1.84 TFLOPS, at a price of $400|
|November 2013||$0.16||$0.17||$170||AMD Sempron 145 & GeForce GTX 760 System||Built using commercially available parts, a system using one AMD Sempron 145 and three Nvidia GeForce GTX 760 reaches a total of 6.771 TFLOPS for a total cost of $1090.66.|
|December 2013||$0.12||$0.13||$130||Pentium G550 & Radeon R9 290 System||Built using commercially available parts. Intel Pentium G550 and AMD Radeon R9 290 tops out at 4.848 TFLOPS grand total of US$681.84.|
|January 2015||$0.08||$0.08||$80||Celeron G1830 & Radeon R9 295X2 System||Built using commercially available parts. Intel Celeron G1830 and AMD Radeon R9 295X2 tops out at over 11.5 TFLOPS at a grand total of US$902.57.|
|June 2017||$0.06||$0.06||$60||AMD Ryzen 7 1700 & AMD Radeon Vega Frontier Edition||Built using commercially available parts. AMD Ryzen 7 1700 CPU combined with AMD Radeon Vega FE cards in CrossFire tops out at over 50 TFLOPS at just under US$3,000 for the complete system.|
|October 2017||$0.03||$0.03||$30||Intel Celeron G3930 & AMD RX Vega 64||Built using commercially available parts. Three AMD RX Vega 64 graphics cards provide just over 75 TFLOPS half precision (38 TFLOPS SP or 2.6 TFLOPS DP when combined with the CPU) at ~$2,050 for the complete system.|
Any researcher at a U.S. institution can submit a proposal to request an allocation of cycles on the system.