|Version||ARCHLVL 2 and ARCHLVL 3 (2008)|
|Encoding||Variable (2, 4 or 6 bytes long)|
|Branching||Condition code, indexing, counting|
|General purpose||16× 64-bit|
|Floating point||16× 64-bit (plus 32× 128-bit vector registers in latest version)|
|History of IBM mainframes, 1952–present|
z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit instruction set architecture implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, and zEnterprise 114.
z/Architecture retains backward compatibility with previous 32-bit-data/31-bit-addressing architecture ESA/390 and its predecessors all the way back to the 32-bit-data/24-bit-addressing System/360. The IBM z13 is the last z Systems server to support running an operating system in ESA/390 architecture mode. However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture will be unaffected by this change.
Most operating systems, including z/OS, generally restrict code execution to the first 2 GB (31 address bits, or 231 addressable bytes) of each virtual address space for reasons of efficiency and compatibility rather than because of architectural limits. The z/OS implementation of the Java programming language is an exception. The z/OS's virtual memory implementation supports multiple 2 GB address spaces, permitting more than 2 GB of concurrently resident program code. The 64-bit version of Linux on System z allows code to execute within 64-bit address ranges.
For programmers who need to store large amounts of data, the 64-bit address space usually suffices.
Applications that need more than a 16 exabyte data address space can employ extended addressability techniques, using additional address spaces or data-only spaces. The data-only spaces that are available for user programs are called:
These spaces are similar in that both are areas of virtual storage that a program can create, and can be up to 2 gigabytes. Unlike an address space, a dataspace or hiperspace contains only user data; it does not contain system control blocks or common areas. Program code cannot run in a dataspace or a hiperspace.
A dataspace differs from a hiperspace in that dataspaces are byte-addressable, whereas hiperspaces are page-addressable.
Traditionally IBM Mainframe memory has been byte-addressable. This kind of memory is termed "Central Storage". IBM Mainframe processors - through much of the 1980s and 1990s - supported another kind of memory - Expanded Storage.
Expanded Storage is 4KB-page addressable. When an application wants to access data in Expanded Storage it must first be moved into Central Storage. Similarly, data movement from Central Storage to Expanded Storage is done in multiples of 4KB pages. Initially page movement was performed using relatively expensive instructions, by paging subsystem code.
The overhead of moving single and groups of pages between Central and Expanded Storage was reduced with the introduction of the MVPG (Move Page) instruction and the ADMF (Asynchronous Data Mover Facility) capability.
Until the mid-1990s Central and Expanded Storage were physically different areas of memory on the processor. Since the mid-1990s Central and Expanded Storage were merely assignment choices for the underlying processor memory. These choices were made based on specific expected uses: For example, Expanded Storage is required for the Hiperbatch function (which uses the MVPG instruction to access its hiperspaces).
In addition to the hiperspace and paging cases mentioned above there are other uses of expanded storage, including:
IBM described MVPG as "moves a single page and the central processor cannot execute any other instructions until the page move is completed."
The MVPG mainframe instruction (MoVe PaGe, opcode X'B254') has been compared to the MVCL (MoVe Character Long) instruction, both of which can move more than 256 bytes within main memory using a single instruction. These instructions do not comply with definitions for atomicity, although they can be used as a single instruction within documented timing and non-overlap restrictions.:Note 8, page 7-27
The need to move more than 256 bytes within main memory had historically been addressed with software (MVC loops), MVCL, which was introduced with the 1970 announcement of the System/370, and MVPG, patented and announced by IBM in 1989, each have advantages.
ADMF (Asynchronous Data Mover Facility), which was introduced in 1992, goes beyond the capabilities of the MVPG (Move Page) instruction, which is limited to a single page, and can move groups of pages between Central and Expanded Storage.
A macro instruction named IOSADMF, which has been described as an API that avoids "direct, low-level use of ADMF," can be used to read[NB 1] or write data to or from a hiperspace. Hiperspaces are created using DSPSERV CREATE.
z/Architecture supports running multiple concurrent operating systems and applications even if they use different address sizes. This allows software developers to choose the address size that is most advantageous for their applications and data structures.
Platform Solutions Inc. (PSI) previously marketed Itanium-based servers which were compatible with z/Architecture. IBM bought PSI in July, 2008, and the PSI systems are no longer available. FLEX-ES, zPDT and the Hercules emulator also implement z/Architecture. Hitachi mainframes running newer releases of the VOS3 operating system implement ESA/390 plus Hitachi-unique CPU instructions, including a few 64-bit instructions. While Hitachi was likely inspired by z/Architecture, and formally collaborated with IBM on the z900-G2/z800 cpus introduced in 2002, Hitachi's machines are not z/Architecture-compatible.
On July 7, 2009, IBM on occasion of announcing a new version of one of its operating systems implicitly stated that Architecture Level Set 4 (ALS 4) exists, and is implemented on the System z10 and subsequent machines. The ALS 4 is also specified in LOADxx as ARCHLVL 3, whereas the earlier z900, z800, z990, z890, System z9 specified ARCHLVL 2. Earlier announcements of System z10 simply specified that it implements z/Architecture with some additions: 50+ new machine instructions, 1 MB page frames, and hardware decimal floating point unit (HDFU).
VM Data Spaces architecture is standard on all System/390 processors.
Computer Associates International is now providing data space technology to VSE/ESA or System/370 users.